The present invention relates to a semiconductor memory device, and, more particularly, to a synchronous DRAM (dynamic random access memory) that performs a data write operation and a data read operation synchronously with a clock signal.
Recently, for higher operation speed, synchronous DRAMs (SDRAM) have shifted from a single data rate (SDR) SDRAM to a double data rate (DDR) SDRAM.
FIG. 1 is a schematic block diagram of a conventional DDR-SDRAM 100. FIG. 1 shows only a circuit related to a write operation. A column address signal AD is supplied to a first input circuit 1a, a command signal CM is supplied to a second input circuit 1b, and write data DQ is supplied to a third input circuit 1c.
The column address signal AD is output from the first input circuit 1a and supplied to a predecoder 3 via a first-in first-out (FIFO) memory 2a. The FIFO memory 2a delays the column address signal AD by one cycle (one clock) of an SDRAM clock signal and supplies a delayed column address signal to the predecoder 3. The predecoder 3 supplies a predecode signal of the delayed column address signal to a main decoder 4 and the main decoder 4 supplies a column selection signal to a sense amplifier 5.
The second input circuit 1b supplies the command signal CM to a FIFO memory 2b. The FIFO memory 2b delays the command signal CM by one clock and supplies a delayed command signal CM to a control circuit 6. The control circuit 6 supplies an activation signal to the main decoder 4 and a write amplifier 7 in accordance with the delayed command signal CM.
The third input circuit 1c supplies the write data DQ to the write amplifier 7.
In the write operation mode, the write amplifier 7 and the main decoder 4 are activated in accordance with the command signal CM and the sense amplifier 5 of a specific column is activated in accordance with the address signal AD. At this time, write data DQ is supplied from the third input circuit 1c to the write amplifier 7 and written from the sense amplifier 5 to a specific memory cell (not shown) of a memory cell array 10.
FIG. 2 is a timing diagram showing the write operation of the DDR-SDRAM 100. In the write operation mode, when a word line activation command ACTV is supplied from an external device as the command signal CM, a write command WR is supplied using the word line activation command ACTV after a predetermined latency period. Further, write latency WL is set in the DDR-SDRAM 100 until write data DQ is supplied after the write command WR has been supplied. For example, when the write latency WL is set to "1", an I/O control signal DQS and the write data DQ are supplied from the external device to the third input circuit 1c one clock period after the write command WR.
The third input circuit 1c acquires write data DQ in response to the rising and falling edges of the I/O control signal DQS. The write amplifier 7, the main decoder 4 and the sense amplifier 5 are activated substantially synchronously with acquisition of the write data DQ, and the acquired write data DQ is written in the selected memory cell in units of two bits in accordance with an address signal AD.
In the read operation mode, a read command RD is supplied from the external device to the second input circuit 1b at the same latency until a write command WR is supplied after a word line activation command ACTV has been supplied. The cell information is read from the selected memory cell in accordance with the address signal AD by the supply of the read command RD.
Thus, in the read operation mode, the read operation is started immediately after the supply of the read command RD. Conversely, in the write operation mode, acquisition of write data DQ is started with the lapse of write latency WL after a write command WR has been supplied, and the write operation is started after the acquisition of data has been completed. Accordingly, the time for the write operation to be completed after a word line selection command ACTV has been supplied is longer than the time for the read operation to be completed after the word line selection command ACTV has been supplied.
In such DDR-SDRAM, to reduce power consumption, it is preferable that the third input circuit 1c be activated when write data DQ is acquired after a write command WR has been supplied. However, write latency is "1", that is, a single clock period. This single clock period is shortened with a high-frequency clock signal CLK. However, it becomes difficult to accurately activate the third input circuit 1c when the write data DQ is input after the write command WR has been supplied. To prevent such inconvenience, if the third input circuit 1c is activated in the write operation mode, power consumption increases along with high-frequency clock signals CLK and /CLK.
On the other hand, if write latency is set long, write data DQ is easily acquired even if the third input circuit 1c is activated after the latency period has elapsed from the supply of a write command WR.
However, in the conventional DDR-SDRAM 100, if write latency is set long, the time required until the write operation is completed after a word line activation command ACTV has been supplied is prolonged. This is because the latency until a write command WR is supplied after the word line activation command ACTV has been supplied is set substantially equal to the latency until a read command is supplied after the word line activation command ACTV has been supplied.